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Recent content by VLSIDesigner

  1. V

    Do we need to simulate post synthesis verilog file ??

    verilog post synthesis In ASIC design, Icaus Verilog just performs RTL simulation, could not do GLS with timing delay. You should use a plug-in tool to integrate to Icarus, e.g. iSDF plug-in but too old version!
  2. V

    How to do GLS simulation ?

    Re: GLS Simulation Thanks Suresh with good information from your blog, keep up the good works!
  3. V

    about ASIC verification

    Thanks for your materials
  4. V

    SoC Encounter Labs Database?

    Hi, under SoC Encounter installation_dir, there are folders: 'bin, BuildGates, data, doc, etc, install, README, share, tmp, tools'. There's no dir 'gift' as you told! Pls. tell me more details or share with link/ftp to download Labs Database! Thanks. Added after 2 hours 45 minutes: sorry...
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    SoC Encounter Labs Database?

    Hi all, I am looking for SoC Encounter Labs Database which contains Labs for practice. This is for SoC Encounter training course. Can anyone help me with link or FTP to download? Thanks in advance!
  6. V

    phd or job after masters engineering

    I think one should distinguish between Ph.D's work and job. Most of Ph.D students at Uni. or in industry perform research projects in new technology or develop a new technique or products which will be applied in future as invention. Job in industry means bachelor or master engineers do a...
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    Effective Current Source Model(ECSM) and Composite Current Source Model(CCSM)

    ccsm ecsm Some materials.
  8. V

    Mentor's ADK with Package IC Nanometer Design

    Does anyone know about Mentor's ADK with Package IC Nanometer Design? Does its Place&Route tool work good for real chip design, not for education? And does anyone have its source to download (free of course)?! Thanks.
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    What is the difference between Assura and Virtouso Layout?

    Re: What is the difference between Assura and Virtouso Layou Another verification tool is Calibre by Mentor Graphics which is most useful for DRC and LVS.
  10. V

    What is the best way to start analog IC design?

    For analog circuit simulation, there is several tools but the most using now are Cadence's tools. These run under Solaris/Linux. If you are professional with these Cadence's tools or Synopsys, you will have much chances to get job in IC design!!!
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