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Hi,
You have not set the path for your PCell Evaluator. :-)
When you are instantiating the PCell( Creating submaster), The Pcell code should be evaluated.
Can you please let me know which library/PDK you are using.?
Thanks,
Chaitra
Hi,
SVDB is a database file getting generated after you run LVS. Which contains the LVS errors and other run details.
There can be two reasons because of that you are getting this error.
1. SVDB path is Incorrect : Verify the path correctly. Make sure the database file generated from your...
Hi,
First find out which diode you need for your design.?
There are many types of diodes, Ndiode, PDiode, Nwell Diode, DeepNwell Diode, RF Diodes, native diodes, Schottkey Diode etc. Again in some of this like Normal Ndiode and Pdiode we have lowVT high VT, medium VT diodes. Again in some...
Hi,
I am assuming here you are getting Latchup Related DRC Errors for your Layout.
These rules are coded to ensure your design should not result in failure because of CMOS Latch up Problem after fabrication.
To overcome these errors in your layout, you need to go for Latchup Prevention...
Hi,
It is not actually this space for this width something like that.
If you clearly understand the CMOS Fabrication Process you will get an idea.
Minimum Width of the metal is to ensure that it should not result in any open circuit during etching process of CMOS Fabrication step.
Similarly Min...
Hi,
Thanks....
I found one univeristy handout which explained this concept neatly.
Here it is
https://www.ittc.ku.edu/~jstiles/312/handouts/The%20Body%20Effect.pdf
Hi,
As per my understanding we can have 3 terminal or 4 terminal mosfets in our Design. Some designs uses only 3 terminal mosfets where we don't want the connection of Bulk ( I can say Substrate connection) . In most of the scenarios we need bulk connection means 4 terminals. So please can...
Hi,
It is better if you give a clear picture of what you are doing.
PCell within a Pcell implies you want to create a hierarchical Pcell. Are you a Pcell Developer Or a Designer?. dbCreateParamInst is a Open Access Database command.
Are you creating a Pcell using SKILL Programming language...
To add more,
It depends on which flow you are referring to.
Anything to do with the logic, algorithms etc comes in frontend.
If you are designing a Digital Design, Then RTL coding, Verification forms the front End.(Ex MicroProcessor). Anything that refers to the Physical design of the chip...
papers on present,past,future of vlsi
How do you say.. ? VLSI is something related to Electronics. Something related to hardware. We started with Vacum Tubes!. Now it is Nano Carbon Tubes!.
We reached almost saturation level in technology scaling down now to 22nm.
People say maximum it can go...
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