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Recent content by vjm16

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    ModelSim Problem: Licensing error

    the system date appears to have been set back Hi all, I have modified the date in my system once and again got back to the same date. From that time, my modelsim is not working on my system. When Iam trying to open it, it says, Licensing error, the system date appears to have been set back...
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    ModelSim PE problem or design problem? Give solution

    bounds of part-select into are reversed modelsim Hi all, I have a piece of code as below. When Iam trying to simulate it in modelsim PE, it is giving me the following compilation errors. Bounds of part-select into 'af_addr_r' are reversed. My code is localparam COL_WIDTH...
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    What is the replication operator ?

    Hi, What is replication operator? Please explain in deep. Thanks vjm
  4. V

    hold time and set up time

    Tsetup >= Tmax - (tcomb + tdff) In the above equation, since tcomb and tdff cannot be changed after the chip is out, we can reduce the maximun frequency that the chip can work and thus meet the setup time violation.
  5. V

    Suggest me a digital design simulation tool

    Re: simulation tool You can use Model Sim Student version.
  6. V

    interview questions can anybody help me

    Normally, when two flip-flops are connected in cascade, with some combinational logic in between and if we give an input at one clock edge, we expect the output in the next clock itself. In multicycle paths, this criteria does not meet. The output will be delayed by some number of clocks.
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    OOPS in System Verilog

    systemverilog oop Hi all, Is it necessary to have deep understanding of oops in order to learn system verilog? (Don't mind, as Iam new to system verilog) Thanks in advance, vjm
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    How to do timing verification?

    Re: timing verification You have timing analysis tools for timing verification like celtic
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    Does ModelSim 6.1 support System Verilog code?

    Dear all, Do ModelSim 6.1 f support System verilog code? Can I load and compile and simulate my design written in System Verilog? Please help me as Iam new to System verilog. Thanks in advance, vjm
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    how to design pata slaver?

    What is pata slaver?
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    can any one tell me about the verifcation

    Hey I too suggest the above two books for verification at beginner level
  12. V

    How to insert a driving buffer in a critical path in synthesis?

    Re: synthesis Thanks satya. The info is helpful for me too.
  13. V

    Need help. ASIC or FPGA?

    If you are in verification, ASIC or FPGA doesn't bother much
  14. V

    Career in ASIC or FPGA verification

    Re: ASIC or FPGA Don't worry. Stay where ever you are and continue to work hard in the field. I think verification is same either it is ASIC or FPGA
  15. V

    writing testbenches by Janick beregon

    writing testbenches + ppt Hey Thanks. Even I could find the book.
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