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Recent content by vj007

  1. vj007

    Looking for 6T SRAM cell simulation results

    If anybody has designed 6T SRAM cell please send the simulation results of that. I also designed a 6T SRAM cell but I don't know what should be the practicle simulation results..
  2. vj007

    Memory Design 6T SRAM cell simulation in virtuoso

    Re: Memory Design satrt reading j. m. rabey the designing is given in that book. then start making schematic in icfb schematic editor.
  3. vj007

    Memory Design 6T SRAM cell simulation in virtuoso

    Memory Design I want to design a 6T SRAM cell. can any one tell me how I can get the simulation results for that. I m using virtuoso for cell schematic design and layout design.
  4. vj007

    Cadence Warning & errors! [Please Help me to understand

    cadence warning this tpe of error through spectre may come due to process technology parameters variations check your process technology file and model.scs file whatever you r making is not according to the particular process technology parameter.
  5. vj007

    transistor sizing in dynamic pfd

    pfd dynamic can any one tell me about transistor sizing in dynamic pfd.required for my project work urgently thanx
  6. vj007

    Fundamentals for proper layouting

    ic layout basic hi MI3talk plz send me the books you have my email id is vijendra07kulhade@gmail.com
  7. vj007

    Links for a Design of a 6 transistor SRAM

    tranzistor a6 -lb hello i m also interested in desiging multiport SRAM cell can you give me your work till now what tools you r using for layout entry ,LVS ,DRC and power estimation.
  8. vj007

    Which is the best tool for layout and simulation at home ?

    Re: Which is the best tool for layout and simulation at home Electric VLSI design system tool can be used for layout entry, DRC, LVS and net list extraction. LT-SPICE tool from Linear Technology Corporation will be used for simulations. all these tools are freeware.
  9. vj007

    SRAM memory cell design

    hello my project is to design and implementation of SRAM memory cell. can any one tell me which cadence tool will be required for layout entry. lvs and DRC. and clock speed and power estimation.
  10. vj007

    analog DLL stability issues

    Re: DLL stability I AM ALSO WORKING ON THE SAME THING WILL YOU TELL ME WHAT YOU HAVE DONE AND FURTHER WHAT CAN BE DONE.I HAVE STUIDED PLL AND DLL BLOCK DIAGRAM FROM WHERE I SHOULD START DESIGNING PORTION ON PAPER.PLEASE HELP
  11. vj007

    how to measure the jitter of the PLL clock in cadence?

    Re: PLL simulation in Cadene I ALSO WORKING IN SAME FIELD COULD YOU HELP ME BY TELLING WHAT HAVE DONE IN THIS FIELD
  12. vj007

    Help about Sparten3E kit

    Can any one help me how to download a VHDL program in Sparten 3E and display the result in lcd display i am succeded in downloading the program but i don't know how to get the display in LCD.
  13. vj007

    cadence tools and there installation in Linux plateform

    Sir what r the back end tools provided by cadence.
  14. vj007

    cadence tools and there installation in Linux plateform

    Hi Friend I have cadence tools in my lab in Linux plateform can any one tell me how to instaal it and run it?
  15. vj007

    embedded VLSI design?

    hi can any one tell me what is embedded VLSI design? thanks
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