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Memory Design 6T SRAM cell simulation in virtuoso

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vj007

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Memory Design

I want to design a 6T SRAM cell. can any one tell me how I can get the simulation results for that. I m using virtuoso for cell schematic design and layout design.
 

Memory Design

Using Virtuoso Analog Design Enviroment.
You can call it from Virtuoso Schematic Editor.
 

Memory Design

basic flow?

any link or doc will be of gr8 help
 

Re: Memory Design

satrt reading j. m. rabey
the designing is given in that book.
then start making schematic in icfb schematic editor.
 

Memory Design

1.make your 6T_SRAM circuit in candence composer;
2.dump a spice netlist(6T_SRAM.spi);
3.write a control file to do a pre_simulation;
4.do its layout in virtuoso;
5.extract RC parameter to do post_simulation.
 

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