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Recent content by vivekniwane

  1. V

    i need the verilog coding of 8051 microcontroller

    First u check out opencores.org and try vhdl to verilog conversion.
  2. V

    Prefer FEDORA for electronics purpopse

    Hi all! If anybody is lookin for electronics tools over linux. Don't waste time in finding rpms and repositories for every software. Use FedoraElectronicLab by Chitlesh Goorah . It's really efficient to use it. You can download it for free from https://spins.fedoraproject.org/ Regards.
  3. V

    what is body effect in CMOS?

    body effect in cmos In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the...
  4. V

    Need of VLIW processor code

    Check this : https://www.opencores.org/projects Regards.
  5. V

    An Automated Analog Layout Generation Flow (ADC, OTA)

    I guess a paper over cmosedu will help u. Here is it's link: **broken link removed** Regards.
  6. V

    65nm spice netlish or schematic

    65nm spice Hi! U'll find it over mosis website https://www.mosis.com/Technical/Testdata/ibm-65-prm.html Regards.
  7. V

    SPICE model and IBIS model

    ibis models versus spice models ads From a manufacturer's point of view, releasing a PSICE model of their component has some risks. Competitors may be able to work out confidential circuit implementations from the netlist. IBIS, or the "Input/Output Buffer Information Specification," is a...
  8. V

    need a spice model for 1um transistor

    Re: spice model I'm afraid that u'll find 1um tech file apart from cmosedu.com. But u also try https://www.mosis.com/ Here u can probably get most of spice tech files.
  9. V

    Hi, I want to design a 1024*32kbytes SRAM array with Hspice

    Re: Hi, I want to design a 1024*32kbytes SRAM array with Hsp Hi there, Best option for u will be to have overlook at https://cmosedu.com/cmos1/hspice/hspice.htm If u r new to hspice u'll find very helping stuff here. Regards.
  10. V

    decision taking gates

    This can be a out put logic level determining module of gates which defines the correct output level for the main module of circuit. This can be just like aTotem pole out put stage for a circuit. Or a controlled inverter in CMOS design. Or a small circuit module in a MUX which controls the out...
  11. V

    8bit CMOS RISC Processor Implementation

    But in road map for CMOS RISC project I have nothing to do with VHDL Implementation. Through VHDL implementation, RTL generated will be completely dependent on the coding efficiency and I think it will not do for me. I want a complete CMOS approach for this implementation.
  12. V

    8bit CMOS RISC Processor Implementation

    Can any of the members please suggest the road map or any guidelines for implementing an 8bit CMOS RISC processor?
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