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Hi, I am trying to learn task and function in verilog. Here's what i tried-
code-
module add_task(a,b,y, clk);
input [3:0] a, b;
output [4:0] y;
input clk;
reg[4:0] y;
always @(posedge clk)
begin
add(a,b,y);
end
task add;
input [3:0] in1, in2;
output [4:0] out;
reg [4:0]out...
Which tool is best for using VERILOG language. Need with simulation. I have been using Xilinx ISE, but there are some problems. Please suggest any other tool.
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