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Recent content by vipul982

  1. V

    Tessent MBIST for memories with dedicated test clock

    Going by details provided by tessent and your lvlib snippet, this memory has internal muxing logic to select functional clock or bist clock. You should be good by defining only MBIST_CLK, mux select line is already controlled by BistEn. I'm assuming that internal muxing is there to gate...
  2. V

    Can you convert GDS file to DEF format?

    Have not tried it but I recommend you checkout magic layout tool and explore if it is indeed possible. Here's the link: http://opencircuitdesign.com/magic/commandref/def.html
  3. V

    identity crisis (Items appearing in home office)

    Doesn't seem to have any optical or microphone components from the image. Do you have any pets or any rodent infested in your home that could possibly bring it from outside?
  4. V

    MBIST DONE & GO failing conditions

    Hi, I want to assess the following condition: If an MBIST controller and memory is intended to run at a functional frequency say 100MHz and a testbench is also generated to run at same frequency, but the frequency that is recieved is 20MHz. How will the failure look like in simulation? 1. will...
  5. V

    vcd file generation for netlist

    need to be done in testbench. lookup for $dumpvars in google for details.
  6. V

    [SOLVED] Hz vs number of bits

    Isn't it possible to add combi logic to represent a toggle enable?
  7. V

    LEC at top level of a SOC

    Hierarchical LEC(bottom up approach) would be faster compared to LEC done by enabling all blocks.
  8. V

    [moved] Learning DFT as an intern and need help with .dft.v files

    Best to start with the book "vlsi test principles and architecture" by Cheng-Wen Wu, Laung-Terng Wang, and Xiaoqing Wen.
  9. V

    using HITEC/PROOFS on ubuntu

    Hi all, I recently got to know about the free test generation/fault simulator tool called HITEC/proofs developed by university of illinois. I was wondering whether I will be able to install it on my personal laptop(ubuntu). Here is the webpage: **broken link removed** Looking forward for your...
  10. V

    Why is write and read levelling technique is completely different in DDR3?

    Hi guys, I wnated to know why write and read levelling technique is completely different in DDR3? are both of them done to synchronize between clock and DQS signal? I am not clear as to why both technique is different even though same result is targeted...
  11. V

    Randomized NRZ bandwidth issue

    Whatr type of filters are usually preffered?
  12. V

    Randomized NRZ bandwidth issue

    Hey there, I am basically modulating a PCM interleaved data using digital technique(PSK, FSK) in LabVIEW. I have read about RNRZ where it is said that the bandwidth needed for it is only 0.7 of the data rate. Now I know that for modulating the bits, we need I/Q symbols, do I have to bandlimit...
  13. V

    Problem with the justification of the ADC result

    Recently i wrote a code for ADC in pic 18f4520 and faced a strange problem. I did all the initialization as per the data sheet and also added an acqisition delay before starting the conversion. I chose vref as Vdd and Vss. the maximum value which i managed to achieve in ADRESH was 0x01 and...
  14. V

    simple adc using pic16f877a problem

    Go for C language, its much easier to control ADC..
  15. V

    DC motor using PIC 18F(microchip)

    you can use l293d for driving simple DC motors, and as far as pic controllers are concerned, it is a high end controller and the data sheet itself has a lot of explanation for initializing ports and other peripherals.
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