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Recent content by vijaysunil

  1. V

    measure gain margin and phase margin

    Hi LvW, Can you please tell why the phase margin is worst in the case of unity gain buffer? Thanks, VIjay
  2. V

    Comparator design Help !!

    **broken link removed** - link in not working, can u pls check. Thanks!!
  3. V

    measure gain margin and phase margin

    20log(Vout) is used to plot the graph. So when u are reading the gain from the graph, it is correct only if the magnitude of Vsin is 1V. Else u need to reduce the gain by 20logVsin to get the correct value. Please make sure that u are doing this when u are varying the magnitude of Vsin.
  4. V

    How to reduce the current in a constant Gm circuit.

    In the desing of an opamp i am using a constant Gm circuit to generate the referece bias voltages to have the desired bias currents in various stages of the opamp( please refer to the pic attached). I wanted to design a Gm circuit that 1. would have a current of 15uA on both the left and right...
  5. V

    Effective or Drawn length

    Thank you very much for the reply. If u understand you correctly, i should be using the drawn length. However, we generally use the value of L, from W/L ratio from the drain current equation, which is the effective and not the drawn length. So, which one do we use. Thanks a lot in advance!!
  6. V

    Effective or Drawn length

    In Cadence, while specifying the length in the properties Window for a transistor should one specify the drawn length or the effective length.
  7. V

    Common mode gain of a diff. Stage with non- ideal current source

    For the diff stage with non ideal current course with current source resistance as Rss.(ckt diagram attached) The differential gain is given by -gmRD. I have biased and simulated the same with Iss = 100uA and Vin(common mode) = 4V. When i did hand calculations, the differential gain comes out...
  8. V

    Change of width and lengh during fabrication

    May i know what % of variation could be expected while a device is fabricated. eg. say i designed a CMOS device with W/L as 100um/1um. Can i expect a variation of about 10% in the fabricated device dimensions i.e. effective W/L becomes 90/0.9 OR is the % variation lesser than this. Thanks a lot...
  9. V

    how to increase MOS gain?

    I have a question, why should it be considered as Current Biasing? We fix the dc voltage at the gate of the MOS, so should it not be considered as Voltage bias? And for a fixed voltage bias gm is inversly proportional to L so an increase in L would increase R but decrease gm by the same...
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