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Recent content by vijaymishra

  1. V

    Layout techniques (Rg reduction)

    Intutively, the layout technique on the left, is like, applying same potential to either ends of a resistor, thereby making them in parallel.
  2. V

    Voltage route consideration

    Thanks for the reply. As this gate route [in metal] increases in its length, there would be voltage drop on the line. What equations will model the voltage drop in the metal path? There should not be a current flow in a voltage path. Is this correct?
  3. V

    Voltage route consideration

    The question is more with respect to the MOS current mirror and not with any other route. The voltage route in consideration is the the metal track connecting the gates of the mosfets in a current mirror. With this scenario the above explanation does not hold good. ---------- Post added at...
  4. V

    Voltage route consideration

    Thanks again. But i disgree that every path is just R. Any metal trace is an RC network and not just R. Had they been just R network, then yes there would have been voltage drop which can be significant to ruin the design. Practically this is not the case. So the question remains the same, how...
  5. V

    Voltage route consideration

    Hi, Thanks for the reply. The question is how is the voltage drop happening? Whatever current flows for the small time duration to charge the capacitor results in the capacitor voltage reaching to Vg. So how is the drop happening?
  6. V

    Voltage route consideration

    Hi, I case of a current mirror layout, the gate voltage line is under consideration. We are required not to route voltage lines for long. As per my understanding, the RC model [per suqare] of the metal track, acts like a RC network for the voltage source [Vgs].Depending on the RC time constant...
  7. V

    Layout of buck converter - need the switch layout

    Re: layout of buck converter Can we have a look at the schematic for the same?
  8. V

    Pipelined ADC Layout Considerations

    what is adc layout Hi, I am to start a new layout on a 15 stage pipelined ADC. What are the specific layout considerations for the same? The design is of a folded cascode opamp, switch cap architecture, a feedback stage. Thanks, vijay
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