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Hi All
I need some help regarding systemC reference model integration in UVM.( tool Synopsys VCS)
Which method is good .. systemc model planning to implement cycle accurate.
1) using DPI calls
2) or use TLM ports
3) any other method
Please provide your ideas if its used.
Thanks
Re: CRC calculation
Hi in this design when i convert polynomial to binary its required 9- bits, but you declared only 8 bits instead of 9.
Can u clarify me.
even for crc-32 also
FCS The CRC is calculated using the following Standard generator polynomial of degree 32:
//G(x) = x32 + x26 +...
verification openings
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Skills
Experience with verification methodologie using HVLs(Specman).
Minimum 2 years experience spanning all aspects of VLSI/ASIC Design using RTL methodology
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modelsim systemverilog testbench
hi,
I want to learn the system verilog..
Where can i get the basic codes..
How to familiar in easy way..
Now i am woking with verilog (cdoing and simulation)
give me some guidelines..
vijay
HI ,
I have some doubts regarding 4-way handshaking.
How the initiator will calculate I-Nonce.
Can you get some idea for PTK MIC calculation.
These are depending on PTK MIC ← PRF-64(K, N, A, B, Blen).
get me some clear picture to immplement the 4-way handshake..
waiting for reply...
ECMA-368 Security
HI ,
I have some doubts regarding 4-way handshaking.
How the initiator will calculate I-Nonce.
Can you get some idea for PTK MIC calculation.
These are depending on PTK MIC ← PRF-64(K, N, A, B, Blen).
get me some clear picture to immplement the 4-way handshake..
waiting...
hi
I am designing one interblock data exchange block to transfer the data between two devices. can any body send some tips and matirials for designing a source and sink to data transfer. i am doing 8 bit serial trensfer. (cmd/bank,address,data1,data2..........cycle wise).only one input and one...
hi
i need some material for how to write test benches and how many types of testbenches are there.
regards,
Mallikarjun,
hi there are somany techniques available.
using task writing testbenches is more reliable.
and insted of hard delays use repeate keyword.
thease are some basic...
hi
Can anybody tell me suggestion regarding scan courage. coverage couldnot meet the expectation . is mainly from which faults.(Is it mainly )because of bridging.
doubts in sta
hi can any body suggest me regarding timing exceptions. How to find out false path.How to set the constrains for the multicycle paths for hold checking.
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