Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hello all,
Is it common in first maskset to tapeout with some WNS on some of the paths? WIll you still signoff STA as ok and go ahead with tapeout.
I understand this depends on the design and how conservative various design constraints are setup, etc etc.
But if the timing constraints and...
RCA,
Thank you for the code for the dual access flop. Is there change of data contention happen when both read and write control signal happen at the same time. This is given that read is async and write is synchronous with the clock. Unless the control unit of the fifo handles it in such a way...
Hello RCA,
What is a dual access flop. Is it a read and write at the same time?
Can you please share any material that you may have on the design of a dual access flop.
Vijay
using VCS
Hello all,
I am new to VCS. I have a crc_tx and crc_rx which calls sub blocks crc5 and crc 16. I also have a test bench written for crc_tx and crc_rx. When I run the vcs command like below, I get error message saying unresolved modules.
How do I need to run the vcs command so it...
It is way of testing out the memory cell by stoing a 10-10 pattern in the memory array, so as to induce maximum stress on the cell. With this kind of pattern a defective cell will have a charge loss or charge gain and the data on the cell might get altered which are caught during subsequent testing.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
