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vera simulation does not start

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vijayatmu

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using VCS

Hello all,

I am new to VCS. I have a crc_tx and crc_rx which calls sub blocks crc5 and crc 16. I also have a test bench written for crc_tx and crc_rx. When I run the vcs command like below, I get error message saying unresolved modules.

How do I need to run the vcs command so it includes all the sub-modules (which are in seperate file)?

Can you please help me out?

thanks..
===================================================
bash-3.00$ ls
command.log crc_5.v crc_tx.v default.svf run syn tb_crc.v
crc_16.v crc_rx.v csrc filenames.log simv.daidir synopsys_dc.setup
bash-3.00$ vcs crc_tx.v tb_crc.v -debug_all
Chronologic VCS (TM)
Version B-2008.12 -- Mon Oct 12 19:16:34 2009
Copyright (c) 1991-2008 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'crc_tx.v'
Parsing design file 'tb_crc.v'
Top Level Modules:
tb_crc

Error-[URMI] Unresolved modules
Instances with unresolved modules remain in the design
Invalid instantiation at: "crc_tx.v", 67: crc_5 tx5(.clk_c(clk_c),
.reset(reset), .halt_tx(halt_tx), .cwe_z(cwe_z), .chck_enbl(1'b0),
.data_in(data_in), .data_out(data_out_5bit), .error( ...
Invalid instantiation at: "crc_tx.v", 77: crc_16 tx16(.clk_c(clk_c),
.reset(reset), .halt_tx(halt_tx), .cwe_z(cwe_z), .chck_enbl(1'b0),
.data_in(data_in), .data_out(data_out_16bit), .int ...
Invalid instantiation at: "tb_crc.v", 41: crc_rx RX(.clk_c(mclk_c),
.reset(reset), .rcs(rx_rcs), .cwe_z(rx_cwe_z), .chck_enbl(rx_chck_enbl),
.data_in(rx_data_in), .select16(rx_select16), ...

CPU time: .029 seconds to compile
 

skyfaye

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Re: using VCS

Just include all your files on the command-line. That's the simplest for your case.
 

vijayatmu

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Re: using VCS

thank you it worked. I think I missed a file when I ran the first time.
 

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