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Recent content by Vignesh_J

  1. V

    SAF capture clocking

    Hi All, Which clock we use for capture pulse in SAF patterns? Fast test clk or functional clock? Also, I can see only one capture pulse for SAF, though we use LOC method in design. Please can anyone explain?
  2. V

    On Chip Clock Controller Working

    Hi everyone, Can you please explain the structure of OCC and how are we generating two capture pulses during scan? Thanks.
  3. V

    Pipelined Scan Enable

    Hi Everyone, I am trying to understand pipelined SE structure for LOS. What exactly that means? Plese can someone explain? Thanks.
  4. V

    Pattern number signal in shm

    I am saying about the DFT ATPG patterns. I am trying to analyse a simulation mismatch of a ATPG pattern with a shm dump file.
  5. V

    Pattern number signal in shm

    Hi All, I am trying to analyse a waveform using simvision loading a shm-trn database. I have dumped the shm file between some patterns. Would there be any signal dumped which can give the pattern number with respect to the time?
  6. V

    Compression ratio

    Hi crutschow As Design, I meant to say for an IP, EDT logic is placed within IP's right? So how compression ratio's are defined when EDT's are placed?
  7. V

    Compression ratio

    What is meant by compression ration and how it is calculated for the design?
  8. V

    Iddq HVST Retention patterns

    What are Iddq, HVST and Retention tests? What would be the differences in the ATPG setup for creating the corresponding patterns from normal Scan ATPG ?
  9. V

    ATPG DRC and SCAN DRC

    What is the difference between ATPG DRC and Scan DRC? Are there any specific DRC's associated with EDT?
  10. V

    EDT pattern simulation

    For EDT patterns, if parallel patterns pass the simulation but serial patterns fail, what will be the reason?
  11. V

    DFT Visualizer Data View

    I see three shift pulse when SE in enabled. So Shift in data of Q 000 means that three 1'b0 are shifted in the scan chain at shift clk right? Correct me if I am wrong.
  12. V

    DFT Visualizer Data View

    Hi I am trying to debug a simulation mismatch. I am viewing the design through DFT Visualizer. I gave the pattern index of the simulated pattern. The visualizer shows 9 bits of data for each pin in the instance. It is something like this. D 000-000-000 Q 000-100-000-[0] What does it mean?
  13. V

    DFT parallel pattern simulation mismatch analysis

    Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI Kindly correct me if I am...
  14. V

    Normal flop to scan flop

    In a scan chain, is only one MUX is added to make it scannable or for every flop one MUX is added? How do the MUX is added to the sequential logic to make it scannable?
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