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Recent content by verma.ind

  1. V

    Linux Keyboard shortcuts

    Hi...... Can anybody tell what is the keyboard shortcut for opening konsole window....... In KDE desktop environment......... Thanks
  2. V

    Floating Point Conversion

    Hi...... Can anybody help me in converting integer or bits to real in vhdl. please Thanks
  3. V

    what is hot-topic in digital design now?

    I think now a days formal verification is the hot topic in atleast verification field...
  4. V

    USB drivers in linux redhat7.2

    Can anybody tell, how to install usb port drivers in linux redhat7.2? Drivers will come with the linux cd or we have to download it.
  5. V

    Regarding PSL Assertion

    Hi..... What is fairness and starvation in verification and how i can check this fairness problems with assertions? Thanks
  6. V

    E as the verification language in comparison with others

    Re: E is the only one? hi can anybody help me. my question is, while doing eVC with eRM methodology we r using sequences for stimulus generation and If we r not using eRM methodology then how can we generate stimulus? can anybody give me brief about it.
  7. V

    What does the precision value in Verilog Timescale represent?

    timescale in verilog is this also related to sampling of input means if u have pulse of less than resolution time, then the simulator will not sample that value?
  8. V

    What does the precision value in Verilog Timescale represent?

    When we define `timescale 1ns/1ps 1ns represents the reference time and 1ps as precision value This reference time is for simulation and delays, but what that precision time represents in simulation and delays? Thanks
  9. V

    Array assignements in verilog

    Hi.... I think u have declare a one-dimensional array and assigning to two dimensional array that's why it's giving an syntax error. What u hv declare is 1-D array of width 8bit..... For 2-D array: it is reg [7:0] arr [7:0][7:0];[/code]
  10. V

    Regarding PSL Assertion

    I am writing psl assertion for interfacing signals from one module to another module. Like if Module A has signal sigA1 which is connected to Module B of signal sigB1, then i have written property prop1 = always (A.sigA1 == B.sigB1)@(posedge CLK); assert prop1; Whether this is the correct way...
  11. V

    Regarding PSL Assertion

    Can anybody tell me is it useful to write assertion for checking the crc?
  12. V

    Regarding PSL Assertion

    At the top level also same problem is coming, i can only access the top module signal, not the instantiated module signal, giving undefined signal error. i will give u one example: "RXActive" is a top level signal and is interfacing signal. .rxactive(RXActive): here i m instantiating the...
  13. V

    Can you synthesize a VHDL and Verilog mixed design?

    Can we write design in both verilog and vhdl means one module of that design in verilog and other in vhdl? Can it be possible? Can we synthesize these type of design? Thanks
  14. V

    How to instantiate a RAM verilog model in the synthesizer?

    Re: RAM verilog model You can check the site www.asic-world.com..... You can get RAM verilog examples in this site.....
  15. V

    Regarding PSL Assertion

    Hi..... I have to check(assertion) interface signals between two modules. Where i can write the assertion so that i can check the interface? I cannot write it any of these module because i will not be able to access the other module signals? Can anybody helps me... Thanks
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