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Recent content by venu pradeepa

  1. V

    how to implement a DFF in verilog?

    dude , try this : always @ (posedge clk ) begin if (reset) q<=1'b0; else q<=d; end Added after 1 minutes: dude , try this : always @ (posedge clk ) begin if (reset) q<=1'b0; else q<=d; end
  2. V

    What is the shift reg and hold reg in UTM

    UTM hi there, I am working on UTM (USB2.0 Tranciever macrocell). can any body (if u worked on that) tell me the shift reg and hold reg part in that, (the serializer) there actually it has "clock domain change " so i have handshaking problem ! cheers venus
  3. V

    Memory initialization for module with 4 FIFOs

    Re: Memory initialization HI, Even I had faced that initialiing problem, coz initial block of verilog is not synthesizable ! so u cant use that . Now for that single step use a frquensy devider as a sub module & call it in ur top module. so u hav devide 25Mhz to 1Mhz...
  4. V

    which style is better

    hi, see there r 3 models in verilog data flow modelling behavioural structural I st one what u have given is data flow II nd one is behavioural the result i.e the hardware of both style is same, but most of the designers use...
  5. V

    What is the difference between ASIC flow and FPGA flow ?

    ASIC & FPGA hi, what is diff b/w ASIC flow and FPGA flow ?
  6. V

    How to constrain design in Xilinx?

    how to constrain design hi, tell me how can i constrain (delays) my design in xilinx. I need complete procedure. venus
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