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Recent content by vasusathiyam

  1. V

    how to calculate jitter for locked PLL?

    please help me..
  2. V

    how to calculate jitter for locked PLL?

    Am new to the analog design. please help me.. how to calculate jitter for PLL(closed loop). am using cadence 6.1.3 version.
  3. V

    Clock shifter by 90 deg

    s i wont change my design further thats y am asking now...... It makes my design to get 40-750MHz output from the PLL..... supply as 1.1V
  4. V

    Help me design a 45 degree phase shifter in HFSS

    Hi , If u dont mine Can u give me your design to get 90deg phase shift
  5. V

    Clock shifter by 90 deg

    i knew tha PLL concept.... r8 nw am also taking second output as QCLK....but i am having the vco tracking upto 500MHz but i need to generate 750MHz without changing the any design like PFD, charge pump , divider and vco in PLL...
  6. V

    Clock shifter by 90 deg

    Hi FvM, of course.... But i done a multiplication using the out delay lines of PLL... After that i am having only one clock in my hand which is 500MHz(Consider this as ICLK)... Now i need QCLK
  7. V

    Clock shifter by 90 deg

    Hi all, Is there any way to shift the clock by 90 deg(only by using digital circuits). Condition: Input is only the clock signal(have to shift)
  8. V

    Problem while locking PLL

    Thanks for all. we get it from simulation only Phase noise is for total PLL or only VCO
  9. V

    MOS should be saturation in transient

    Can anyone tell whether all mos should be sturation in analog circuit while analyzing in transient response?
  10. V

    Problem while locking PLL

    Here i attached the control voltage to the VCO of PLL. From this i know my PLL(2nd order PLL) is going to lock that is the input of the VCO well known from PSS analysis. But i got some oscillation while locking the phase of the signal(2nd wave) (Measured by delta cursor i got 500MHz but in...
  11. V

    current mirror length

    how to make constant current in current mirror? whether it depends on load ? can any one tell the length should be equal in current mirror?
  12. V

    in differential amplifier to single ended

    thanks to all. @dgnani i cant understand what did u said? ---------- Post added at 12:53 ---------- Previous post was at 12:47 ---------- in a differential amplifier how to make constant gain? Gain is varying whenever CMR changes?
  13. V

    in differential amplifier to single ended

    how to find dc gain in differential amplifier in cadence tool? And whether both(ac and dc) gain should be equal?
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