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Ahyma,
As starter I will suggest you to do calculations and assure transistors current carrying capacity.(in the case of M1/M2 and M9/10). You can start the design with all the transistors width of 10um and Length 500nm. You need to take help of any opamp designing book.
4uA biasing current is...
Width should be in Micrometer. Check the aspect ratio for M10 and M1/M2
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Did you do some mathmatical calculations for your design for 4uA bias current. I doubt that.
You are telling -13V output will be loaded to supply. I wonder what combination would have been for resistance and to the supply.
Anywys, if offset is there, OPAMP will be active and it will have constant leakage from +15V to -15V, even though there is 0V input.
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Hi...
Use current mirror based active load for more linearity. or current source for more linearity. There are other technics also to imorove linearity. Please Elaborate more about your requirement and application.
Hi gvardan, this is not strange. I assume your board connections correct, sweep the positive terminal voltage from 0 to 5 volt and find the output when it becomes positive.
I think, some offset in OPAMP is affecting your circuit.
Find out the BETA of the transistor from spec, Find the wattage of the bulb (decide how much current you want in bulb).
Ib=Ic/BETA. YOu know the base current, decide the base resistance accordingly.
No actually reverse is true.
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I think first circuit is better than later. In the second circuit you do not get any gain, because base current is already very high ~2A (~loss), while first circuit carries only collector current and base current is minimum.
First circuit shall...
Hi mjbreddy, you already got correct reply from crushow, when you ask what are Vo1 when Vin is 5V, 3V, 2.5V and 0V.
Another question should be, what would be operating region for transistor across voltage range you specified?
Answer is transistor remain off until Threshold voltage(at gate), and...
Hi Diarmuid,
Channel Length modulation (LEMBDA) is process defined and is generally higher for PMOS compared to NMOS.
Saturation resistance depends upon LEMBDA and Drain current. Drain current again is defined by mobility and W/L.
Since Mobility is more dominant than LEMBDA (this is aprox. same...
Re: Cadence spectre?
Hi Zahrein! how you simulate -25? If you use ADE there should not be any problem.
But from script, sometimes negative numbers are not passed to spectre. Try to put bracket and then try.
May be I am not the correct person to ask.It all depends upon how many bits used to execute the Paint or notepad. These are very small applications. and may be 8 bit used to execute it.
Please try to google JPEG forums for more detail.
Let me explain what I understand from your question.
Software is just codes and when it converts to machine language it is loaded in resistors(flip-flops) as 0 or 1's.
In this manner, the loading of all registers/ (F-F's) will be equal to (no of F/F *current consumption for single Flip flop)...
Hi Walkura, first you should not confused with BJT characteristics with MOSFET.
In MOSFET no term is like active region as in BJT. Active region in BJT off course occurs between OFF and SAT when in ID, VGS curve.
But Id vs Vgs curve for MOSFET, triode region comes ( miss spelt by linear...
Hi gone,
Buffer is just to provide delay, to input data. generally it does not provide voltage gain but current gain so that it can drive the load sufficiently.
When you say level shifter, it means buffer voltage needs extra dc voltage level at the output to drive. Then buffer toplogies uses...
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