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Re: Virtuoso LAyout & different analog and digital groun
Yes of-course there is a solution.
Generally we see this type of connections in each and every layout. Basically this problem we will see only with NMOS, as anyway PMOS bulks are always seperate!
According to the process you are using...
Ok, I myself found some answer!
"A symbolic device is an instance of a parameterized cell that has been defined in the technology file." from Virtuoso® Layout Editor User Guide
Please share if anybody has any more information.
I am more interested to know about how it helps in Layout database...
Folks,
I am working with cadence virtuoso layout editor. When I am using contact types, I am seeing that they are not made by pcell layout but they are done in different view name called "symbolic".
Can anybody please tell me what is this view and why it is used?
if possible give me some...
Re: current handling of vias
It will be definitely individual. You have to calculate the No. of Vias as per the current flowing between the particular metals you are concerned. (i.e. for No.of Via2s, you have to consider the ME3)
Correct me if I am wrong.
Varma.
Hi,
I am not a circuit expert. But as per the experience better to consider the peak current as definitely average current will be less that the peak current!
If you follow peak current, I don't think you will find EM violations neither IR drop issues! Please correct me if I am wrong.
Varma.
Re: off-grid problem
I don't think....We can fix the Off grid problems..for 45 degree bending....If K_90 can eloberate on what he is talking about it will be gr8...!!!
Re: Creation of Pad frame
In DRD from foundry, At pad related rules sections, They will clearly describe the pad structure and layer description. If you have any doubts then...we can discuss...!!!
Re: resistance of path
As per my knowledge...You need not to calculate the resistance by calculator...write a simple perl script which will take width and length of the trace and it will help you alot...!!!
Also somebody mentioned "To take the VIAs into account while calculating the...
Re: 45 nm layout challenges
Deepak can you give more info about these effects that you have mentioned. Becuase I don't aware of these perfectly....Also try and mention the prevention techniques also...!!!
45nm
As per my knowledge, Going to down technologies following are the some of the issues we critically find out....
1. WPE
2. LOD
3. Density.
4. Lot of DFM and Yield related rules.
5. More conservative OPC rules.
These are upto 65nm. But coming to particularly 45nm, In some of the foundries...
lvs is a short
Ravi chandra,
Give some brief idea to find out VDD VSS short in block level, IP level, and chip level.
It will be usefull for everyone.
Varma.
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