Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
In the design which i'm working on, there are several macros. And due to insufficient spacing between two macros vertical edges the tapcells were wrongly plaed. And these tap cells are overlapping VSS stripe.
What is the issue caused due to this overlap, like any DRCs? Is there any...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.