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Recent content by vaibhava

  1. vaibhava

    Interconnect Delay Vs Clock Period

    Hello Varun, can you please clarify on "does the clock will escape ?" Moreover what is the design intent and the tool being used? Best, vaibhava
  2. vaibhava

    Synopsys DC: Tracing clock path

    Hi all, I'm a beginner with Synopsys DC. I synthesized a particular design and later defined and propagated the clocks via the clock ports into the design. Now, I want to trace the clock tree. In particuar, I wish to do the following: 1. Get the cells in the the clock path (I've tried...
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