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Synopsys DC: Tracing clock path

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vaibhava

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Hi all,

I'm a beginner with Synopsys DC. I synthesized a particular design and later defined and propagated the clocks via the clock ports into the design. Now, I want to trace the clock tree. In particuar, I wish to do the following:

1. Get the cells in the the clock path (I've tried get_cells -hierarchical -filter "is_combinational==true" -filter "pin_on_clock_network_per_scn == true && direction==in". Is this the correct way?)

2. Visualize the clock path on GUI (I haven't got a clue on this)

Moreover, i would appreciate if you could suggest some references for beginning with DC.

Thanks in advance!!
 

ThisIsNotSam

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Do you mean visualize the clock tree? It is not implemented during logic synthesis, only later in physical synthesis. I have a feeling you are looking for something that isn't there yet.
 

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