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Hi guys,
Following figure shows the characteristic of a linear PD [1], What will happened if the phase of the clock is between 0ps~10ps or 90ps~100ps?
Papers and textbooks seldom discussed about it in that situation.
[1] J. Savoj and B. Razavi, "Design of half-rate clock and data recovery...
Hi,
I am new to high speed circuit design, I want to design a 5Gbps clock and data recovery circuit using TSMC 0.18um tech, which model of transistor should I use to run pre simulation?
RFNMOS or just nmos? It have warning about model accuracy when I untick the guardring of rfnmos.
Hi guys,
I want try to design some serdes circuit but I have some problems about the standard of SONET. Where can I find SONET specification standard(mask of Jtol and jitter mask of clock and data etc..)? I found nothing on internet, only some brief information from wiki and lectures.
Thank you
Hi guys,
I am new to high speed design, recently I am trying to layout a 5Ghz circuit using tsmc180nm tech. When starting layout using rfmos of tsmc, all of the rfmos have guard ring added by default , I wonder if it necessary each of the rfnmos have guard ring?
or lets say we have a main...
Hi,
transient operating point of M12 and M14,
and
I discover these warning when I run the transient simulation of V/I converter, does this matter?
thanks.
Hi guys,
I tried to reproduce a 5Ghz clock and data recovery circuit from a IEEE paper,
when I design v/i converter I found that in DC simulation the result is fine but in tran simulation have some problems. I wonder is this normal or not?
schematic of v/i converter:
M5 provides 500u A current...
Yeah, the R2 should be replaced by R1 which looks like the pic below (taken from the Dean Banerjee PLL).
Sorry I don't get the point, do you mean I can run the loop analysis of the dual loop system as one loop system?
Thank you
Thanks you for the reply,
pic.1
pic.2
pic.3
pic.4
I would like to design a clock and data recovery circuit, and I am confused by the dual loop system. Usually phase locked loop text book only discuss about single loop system as we see from pic.1 and the filter function is pic2. I would...
Hi,
As I know this type of loop filter is very common, it can found from lot of textbooks and thesis.
But what is the purpose of above graph(a connection to node between resistor and capacitor)?
Is the transfer function still same as 1 path current injection? if not how to find the transfer...
How to do frequency response simulation for inductor peaking in cadence?
I want to design current mode logic with inductor peaking, from the textbook I know that I should run frequency response for it to choose the inductor value, but how to do the simulation?
Best regards.
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