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I am no engineer. I only have fun in understanding how things are working.
Agreed. First I read your post, and THEN I searched the internet ;)
What I understand now:
I) the number of transistors in series between (+)/(-) and output directly affects switching time
II/III) p-type must be on...
Every resource I found in the internet says, that:
I) 4-input AND can only be done by 3 NAND/NOR gates in a tree-structure
II) to get a single AND, the only way is to combine NAND and inverter gates
III) there are constraints where n-type and p-type transistors can be used
Can you explain why?
I have an AND gate with 4 inputs. How could this be implemented in CMOS with minimal switching delay?
(+)
|
input 0 (inverted) -----+-- <--
| |
input 1 ------------+------ -->
| | |...
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