[SOLVED] CMOS design question

[user7813]

I have an AND gate with 4 inputs. How could this be implemented in CMOS with minimal switching delay?

                            (+)
                             |
input 0 (inverted) -----+-- <--
                        |    |
input 1 ------------+------ -->
                    |   |    |
input 2 --------+---------- -->
                |   |   |    |
input 3 ----+-------------- -->
            |   |   |   |    |
            |   |   |   |    |
            |   |   |   |    +----+----+----+----+------ output
            |   |   |   |         |    |    |    |
            |   |   |   +------- -->   |    |    |
            |   |   |             |    |    |    |
            |   |   + --------------- <--   |    |
            |   |   |             |    |    |    |
            |   +------------------------- <--   |
            |                     |    |    |    |
            +---------------------------------- <--
                                  |    |    |    |
                                 (-)  (-)  (-)  (-)

There are at least 3 things, where I am not certain if it will work:
I) can I put 4 transistors in series, or does this require 4 times the voltage?
II) can I turn NAND into AND, simply by swapping (+) and (-)?
III) can I invert the input signal by changing the type of transistor?

no I have no chip design experience, but I have done some VHDL so far.

 

[dpaul]

In very simple and top level terms, to have min. sw. delay use a min. no. of transistors in your design. Have you tried building various configs of the 4 i/p AND gate in your CAD tool and then measuring the delay in each case?
And how to build a 4 i/p AND gate using pMOS and nMOS transistors is covered in any basic graduate level VLSI test book.

 

[user7813]

Every resource I found in the internet says, that:
I) 4-input AND can only be done by 3 NAND/NOR gates in a tree-structure
II) to get a single AND, the only way is to combine NAND and inverter gates
III) there are constraints where n-type and p-type transistors can be used

Can you explain why?

 

[dpaul]

Initially you had some set of questions, and now they have changed!
You mention in the above post "Every resource I found in the internet says, that:..........."
So first let me ask you an honest and direct question. What is it you really want? -- some problem you don't understand or do you want us to explain & qualify for something which you have already found in the internet?

Going with your original question, as I have understood, your problem is to design a 4 i/p AND gate that is having min. sw. delay. I have already mentioned to use the minimum no. of transistors.
If I were the designer, I would use the very basic approach of a 4 input NAND (4 pmos & 4 nmos) connected to a NOT/inverter (1 pmos & 1 nmos) gate. Voltage shouldn't be a big problem for just 4 inputs (experts should correct me if I am wrong here).

As for your other questions, I repeat, please study and *understand* your graduate level analog CMOS design or VLSI design textbook. Please go back and understand your basics.

 

[user7813]

I am no engineer. I only have fun in understanding how things are working.

Initially you had some set of questions, and now they have changed!
You mention in the above post "Every resource I found in the internet says, that:..........."

Agreed. First I read your post, and THEN I searched the internet

If I were the designer, I would use the very basic approach of a 4 input NAND (4 pmos & 4 nmos) connected to a NOT/inverter (1 pmos & 1 nmos) gate. Voltage shouldn't be a big problem for just 4 inputs (experts should correct me if I am wrong here).

What I understand now:
I) the number of transistors in series between (+)/(-) and output directly affects switching time
II/III) p-type must be on the (+) side, n-type on the (-) side

Can you confirm this?



PS: Now I use 3 parallel NAND/NOR/inverter trees and multiplex by a skewed clock to achieve the same result. However, the original question is still interesting to me.

 

[dpaul]

What I understand now:
I) the number of transistors in series between (+)/(-) and output directly affects switching time
II/III) p-type must be on the (+) side, n-type on the (-) side
Can you confirm this?

I> It is not b/w the +/- rails. The no. of transistors (also logic gates) in the path from the i/p to the o/p affects the switching time.
II/III> Yes

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