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Hi,
I am using MOSIS 0.35um process. While doing the layout, after DRC i am getting the following errors.
1) LATI. 3A N-Well PICK-UP to PMOS max space < 20um
2) LATI. 3A P-Well PICK-UP to NMOS max space < 20um
Can anyone help me solving these errors.
Thanks in advance,
Hi,
I would to know the effect of (W/L) on the transistor characteristics.
i.e., even though if we keep the ratio same, how would different (W/L)s effect the shape of the transfer curves of the MOSFET.
Ex: (6/2) , (12/4), (24/8) etc. In all these examples the ratio is 3 but the...
Hi,
I have a temperature insensitive current reference . I want to generate a temperature insensitive voltage reference using the current reference i have. I wanted to do that without any OP-Amp and resistors. Can anyone help me in developing this circuit. I need suggestions about how to...
hi.......can anyone suggest me a few topics for my master's thesis in the field of analog ic design......
urgent.....please help me out...
Thanks in advance
Output stage for op-amp
hi,
I have designed an op-amp to use it as part of another circuit.......but i am having a problem with that.... it is having loading effect......i mean the output voltage is varying depending upon my load value...... this is not acceptable for my use......
So can...
connect one of the input to some dc voltage....then connect the other input to an ac source with the same dc bias and give it a little swing...
For example:
fix Vin+=1.5V
Vin-=0.1V swing with dc bias of 1.5V
now you get the output
plot the magnitude and phase response....
now observe the...
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