Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: Propagation Delay
I guess you're talking about the max freq of a board, not of a chip. For a board, if the clocking scheme is system synchronous, the propagation delay(accurately, flight time) determines the max freq of your board; while if the clocking scheme is source synchronized, by...
ff setup high violation
First let the tools synthesize the design with higher effort, if it doesn't work you'll have to go back to modify your RTL code. To break the worst path into 2 parts by inserting a FF in the middle, or, just latch some signal before using it if the it's ok with your logic.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.