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Recent content by umagne

  1. umagne

    [SOLVED] Subthreshold CMOS Bandgap circuit

    IEEE Xplore - A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference
  2. umagne

    Design of an OTA in Subthreshold

    Since February 2011 it'll be available on JSSC the design methodology of Subthreshold Voltage References, its DOI is 10.1109/JSSC.2010.2092997
  3. umagne

    Urgently,about subthreshold circuit design in CMOS process

    Since February 2011 it'll be available on JSSC the design methodology of Subthreshold Voltage References, its DOI is 10.1109/JSSC.2010.2092997
  4. umagne

    Subthreshold analog design

    Since February 2011 it'll be available on JSSC the design methodology of Subthreshold Voltage References, its DOI is 10.1109/JSSC.2010.2092997
  5. umagne

    Need IO and pad open size of TSMC018um

    Re: IO PAD Size... 65um x 65um. However for more specific information about pad layout try to see the documentation, there is a bonding pad layout guidelines document very useful. By.
  6. umagne

    UMC 0.18um MOSFET abutment

    Hi everyone, Does someone knows if the PDK UMC 0.18um RFCMOE supports auto-abutment for MOSFETs? In the user manual of the foundry I read that it is supported surely for the 90nm node, but after using this technology I discovered that either it is not supported or I have to activate it in some...
  7. umagne

    Chaining transistors - interdigitating the 3 PMOS

    Re: Chaining transistors yes L=50um. This mirror is embedded in a current reference and I found that the sensitivity to power supply variations lower using long channel for those transistors not diode-connected. Do you think is a bad idea to use so long channel? Why? Added after 2 minutes...
  8. umagne

    Chaining transistors - interdigitating the 3 PMOS

    Chaining transistors I'm trying to layout a current mirror and I have some doubts. It's a simple PMOS current mirror (2 transistor M5 and M7) that mirror the current on an additional PMOS (M9). the widths and lengths are: W5=8um, L5=50um W7=8um, L7=50um W9=24um, L9=50um 1) it's useful according...
  9. umagne

    Analog layout - Cadence

    analog auto place and route How can I see if my Pcell (transistor) supports abutement or how can I activate this feature on the pcell of my design kit? Thanks
  10. umagne

    Analog layout - Cadence

    anlog layout interdigitate design I don't think I'm using the Schematic-Driven Layout, I use Virtuoso XL: given a schematic Entry, I create the layout from the command Generate From Source. The system places the transistors separately, I'm asking if there is an option to make interdigitate...
  11. umagne

    which bandgap structure is better

    Could you be more specific. How do you recognize the loops and how do you evaluate if the loop gain is >/< 1. Thanks.
  12. umagne

    Analog layout - Cadence

    cadence layout automatic placing and routing Hi everyone, I'm new to (analog) layout and I'm trying to start my new activity with a standard voltage reference. I use a 0.18um technology with the Cadence environment (in particular the section Custom IC Design). Starting from the schematic entry...
  13. umagne

    which bandgap structure is better

    How do you recognize the loops inside a voltage reference? Could you suggest me some references/books where I can find informations on circuit loops about voltage/current reference? Thanx
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