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Hi Wesley,
Thanks, Yes I am using xilinx ultrascale which have axi bus pci ip core.
Can you please help me understand "You can then have an controller in the fpga which has certain to certain inputs." this.
What I understood so far, is that I have to configure 1 pci IP as master in one fpga...
Hi all,
I wanted to establish a communication between 2 fpgas connected to the motherboard of a pc on 2 seperate pcie slots.
Can I send some packets from FPGA1 to FPGA2 without getting the cpu involved ?
Can anyone please share where can I fond the information / documents regarding the same...
@Tricky,
I Agree, loo much combinatorial, as the rtl was meant for ASIC . cant do much on that front. I mean cant pipeline.
Also the device utilization has gone up to 82% on this Stacked silicon device
Hi Barry,
The speed is 20 MHz
I have some Multicycle path constraints. Do you mean area constraints? I havn't put any area constraints.
Will try all synthesis and par strategies . Thanks.
Xilinx fpga ultrascale vivado 2016.2
The design is utilizing 80% of the device and earlier it used to route with =synthesis stratagy - flow alternate routability & congestoion spread logic high for implementation
now I had to create a small 4 bit counter in the top module and the design is...
help in understanding code ( verilog )
Hello All, I am very new to System verilog and I do not understand the code below. i.e. after 1 bit hold and 128 bit Out has been declared as logic, what is CGlobal CGlobal(); means ?
Also after that, what does the assign statements do here. i.e. clkA is...
I am using Vivado 2016.2 , and virtex ultrascale.
My design is successfully implemented, now I want to increase the frequency of the design by modifying mmcm out clock from 50 MHz to 75 MHz, or if I need to add some false path or multicycle path constraint in the the implemented design, then in...
Re: how to reduce conjestion in a perticular clb
yes I am using virtex ultrascale. as you mentioned the tool is spreading many blocks in multiple stacked silicon. But when I try to partition the design, specifying the pblock for critical blocks, the congestion on other modules increases. also...
Re: how to reduce conjestion in a perticular clb
sorry for the delayed response. My design is failing in routing. there are more than 25000 nodes overlapped and in vertical congestion matrix there is more than 100% utilization. so how can I reduce this congestion ?
how to reduce conjestion in a perticular clb
Is there a way to reduce congestion in a perticular CLB. If I have a report that says the top ten most congested CLBs are CLE_M_X74Y125 and CLEL_RX74Y125 ?
what can I do with this information to reduce congestion in the design ?
Hello all ,
There are times, when I am not allowed to change the RTL, and all the clocking structure in the design are already optimized.
Still I face situations where I have negative slack ( setup as well as hold )
Some times by trying few strategies in Vivado, the tool solves the timing...
In Spartan 3e board 50 Mhz would be the external clock, oscilator frequency. The global clock would be the clock routing in your design through global clock buffer. if you are using DCM/mmcm then the output will automatically routed through global clock buffer.
Hi,
\The Global clock is the main system clock routed through global clock buffer which is uses optimized rotes dedicated for clock. Local clock are the bifurcation of the global clock and routed locally inside a clock region.
Hello all,
If I dump a bit file into an FPGA with no violation and no error and critical warning.
Now if the design is not working, then what are the steps should I follow.
Also if for some reason I cannot use ILA, then what options do I have? How to find the issue where to start from? Is...
How to introduce small delay in clock path ?
Hello all,
How can I add a small fixed ( known ) delay in clock path manually in fpga ?
suppose I have a setup violation and there is no hold violation , then can I add some delay in the clock path between the register to give some extra margin for...
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