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Recent content by ujas

  1. U

    warning: verilog 'assign' or 'tran' statements are written out. (vo-4)

    Yes man. You'r right. So is there way i can fix it ? 18m.v is TSMC header file provided by university.
  2. U

    warning: verilog 'assign' or 'tran' statements are written out. (vo-4)

    Hi Its my bad. Here is the error I'm getting in Modelsim when simulating gate level netlist. 18m.v is header file which has all basic cells. Please tell me what you think about this error:
  3. U

    warning: verilog 'assign' or 'tran' statements are written out. (vo-4)

    I mean after i synthesize all modules , In synthesized netlist, comparator comes with assign statement. Please check synthesized netlist. Did you see? Thanks man for reply.
  4. U

    warning: verilog 'assign' or 'tran' statements are written out. (vo-4)

    Due to assign statement, post synthesis file is not working with testbench. comparator module has assign statement. how can i avoid assign statement? in synthesized why tool gives 4 counter module ? its supposed to be 2 counter. synthesized netlist with TSMC 0.18um
  5. U

    cadence virtuoso layput editor problem

    I can draw rectangle but i can not move , copy or stretch it . Any way to solve this ? Thanks for your time.
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