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Recent content by r1caw ex ua6bqg

  1. R

    Pass VCS filelists into Synopsys SpyGlass

    Hi all, I have RTL project; for VCS simulation I have a set of VCS-style *.f filelists with includes, include directories and RTL files with path to them, smth like this: ## general filelist ################ ################ +incdir+${ROOT_DIR}/dir1 +incdir+${ROOT_DIR}/src/dir2...
  2. R

    Master data width is more than slave data width in Qsys AXI bridge

    Yes, I already tried to implement AXI interconnect with 128bit master<->32bit slave, and it does not work. Then I have searched in the Intel documentation, and found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not...
  3. R

    Master data width is more than slave data width in Qsys AXI bridge

    Thank you very much for your answer! Maybe someone knows way to do that using Qsys IP cores?
  4. R

    Master data width is more than slave data width in Qsys AXI bridge

    Master data width is more than slave data width in Altera/Intel Qsys AXI bridge Hi all! Currently I am working in Quartus 17. I have created AXI bridge-based system in the Qsys, where data bus for both master and slave sizes is 32-bit. Now I need to increase AXI bridge data width to 128 bit...
  5. R

    Different operating conditions in the MV and design libraries

    Thank you for your answer! Yes, I understand. But this is the libraries from one PDK from well-known vendor. Actually, say, for design library with VDD 1.2V name of the op_cond in the lib file is "op_cond_A". For the MV library with level-shifters from 1.0V to 1.2V there is op-cond name is...
  6. R

    Different operating conditions in the MV and design libraries

    Hi all! I want to create Multi-Voltage design in DC. As I understand, I need to use some specific cells for power gates, level-shifters, etc. The problem is that library for these cells has different operating conditions (names of the op cond in the lib/db file) than library for normal cells...
  7. R

    Need a answer for below problem in static timing analysis

    FYI - try to find this book, "Static Timing Analysis for Nanometer Designs - A Practical Approach". it is well suitable for you task. Also you can find in the web information about setup and hold timing calculation.
  8. R

    Variable in Design Compiler for clock gating

    Can you, please, elaborate in which situation it can be bad?
  9. R

    [SOLVED] Common POLY layer in the digital standard cells

    But what this CUT layer do with POLY layer, if it will be assigned to the POLY layer? Cut it during manufacture of the chip?
  10. R

    [SOLVED] Common POLY layer in the digital standard cells

    Thank you for your answer! Can you, please, elaborate why do we need this "cut-POLY" layer?
  11. R

    [SOLVED] Common POLY layer in the digital standard cells

    I cannot show real layout due to NDA. In real layout I can see wide (much wider then gate POLY) POLY layer in the upper and bottom parts of the cell - exactly as in the picture. Any ideas? I have checked in ICC - this is POLY layer.
  12. R

    [SOLVED] Common POLY layer in the digital standard cells

    Hi all! I have a question related with the standard cell layout. I have revised 28nm digital stdcells layout obtained from foundry and I am little bit confused - in this cells POLY layers (gates of MOS) are connected together in the upped and bottom parts of the cell (looks same as in the...
  13. R

    UMC 65nm without TLU+ files

    Dear all! I have UMC 65nm CMOS library to perform synthesis and PnR in Synopsys tools. I have revised this library and found that there are no TLU+ files (without TLU+ files I cannot perform DC-topo synthesis and PnR in ICC). Moreover, there is no .itf file to convert TLU+ files from it. How I...
  14. R

    DC-topo and ICC environment comparison

    Thank you! But I am always work in DC-topo. What do you mean when talking about placer and router in ICC?
  15. R

    DC-topo and ICC environment comparison

    Thank you for your answer! Unfortunately, I am talking about ns, for example, -0.22ns for DC-topo and -0.47ns for ICC. Why I get this huge difference?
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