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Recent content by Tychus

  1. T

    [SOLVED] post Synthesis simulation problems

    ads-ee suggestion fixed the issue. I'm not just clicking buttons this is not what i do for a living nor what i want to do this was dumped on me with a set of instructions that serve nothing the whole problem is the red line i do not know what it is or why it is there that is why I'm asking you...
  2. T

    [SOLVED] post Synthesis simulation problems

    If this can be of any help cadence throws these warnings after the elaborate command:
  3. T

    [SOLVED] post Synthesis simulation problems

    Here is the waveform from netlist simulation as you can see it does not generate the fibonacci series like the post synthesis simulation. would you like me to include logs from cadence, ads-ee and thisisnotsam suggested i fix my rst in testbench i have no idea what to fix and how i...
  4. T

    [SOLVED] post Synthesis simulation problems

    Ok here's what happens simulating the netlist generates clock signal, the limit signal also carries the correct value. the output remains red even if i simulate for 1000ns. XXXXXXXX i attached an image of vhdl simulation (the one that works) the last signal is what i'm having problems with. hope...
  5. T

    [SOLVED] post Synthesis simulation problems

    like i said the simulation does not generate ANYTHING output does not carry any value. i believe i answered that in the first reply
  6. T

    [SOLVED] post Synthesis simulation problems

    I don't know what an RTL simulation means i was given instructions to synthesize with cadence and simulate with modelsim both before and after synthesis. this is the testbench i'm using testing the vhdl design generates correct output but simulating verilog netlist doesn't. library ieee; use...
  7. T

    [SOLVED] post Synthesis simulation problems

    After synthesizing the design i get a verilog netlist file which i simulate in modelsim; the simulation does not give any output.
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    [SOLVED] post Synthesis simulation problems

    Hi all, I'm having problem with my design (fibonacci generator) i've been trying to fix this for the past few days in vain. I'm using Cadence RTL and Modelsim for the simulation. The netlist generated from this give no warnings or errors but still doesn't simulate right anyone can give some...
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    [SOLVED] Help with synthesis signals and sensitivity list

    Hi, I'm a newbie when it comes to VHDL, synthesis and all what goes with. I'm having hard time with an assignment where i have to design a Fibonacci generator. i wrote a code with a test bench everything working fine until i tried to synthesize it using cadence; i got two warning messages that...
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