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Hi,
I Attached schema with 3 MOSFETs that prevent from capacitors C34, C35 to charge at 3 different time interval.
Do you think that MOSFETs can be damaged from from differnet timing of satuartion for each MOSFET ?
I put a Diodes that protect from situation that the capacitors charge for...
Hi,
See attached, i want to measure the voltage signal between A to B with scope , i have a conventianal scope (not floating).
The hook of the probe of the scope i connect to A, Where do i need to connect the ground of the probe ? to B?
Thanks.
There is no data on reproducible timing behaviour.
I built 4 identical circuits and measure and receive: 604.23 , 603.39 , 608.99 , 607.3mSec.
The average value is far from calculate delay: 640mSec.
The tolerance of the resistor and capacitor are 1%, but the time difference is very large.
I do not need a accurate timer, i want to understand why there is large deviation.
Hi,
I buit the attached timer and receive a delay of 604mSec instead of 640mSec, How can you explain ?
n=13
2^(n-1)=4096
VCC=+16VDC
The mesurement of the Delay is between VCC start up to change state at the OUTPUT.
Thanks,
Hi,
I use comparator from ON-SEMI pn:NCS2200SN2T1G ,
In the attached data sheet it is write the the range of common mode voltage VEE to VCC:
but in the Graph the CMV Range is smaller and not reach to supply voltage:
How can you explain this CMV difference ?
'373 Latch is Octal and big IC i need only 1 DFF.
1650372530
The Recovery Time: /C to CP for pn:NL17SZ175DBVT1G acc. the data sheet is minimum 1nSec over temperature, So it is look that i need to add RC circuit at CP Input.
Note that when used as a comparator, only one input needs to be within the common mode range. The other input can be above the common mode range or above VCC and the output will be the expected VOH level (for Vin+ > Vin–) or VOL level (for Vin – > Vin+)
Phase Reversal occurs when the input of...
Hi,
I want to memorize the state of a switch, see attached schema, i connect DFF from ON-SEMI pn:NL17SZ175DBVT1G to the switch, the D input will move to Q output at rising-edge of CONTROL signal CP, i dicide also to connect /C input to CONTROL input in order to insure the Q=0 when CONTROL=0...
We have a lot of problems to purchase IC in these days so if we have IC that already in BOM and available it will prefer.
I increase the VCC voltage from other regulator.
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