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Re: 8 8 bit resgister
if i use indexin : in std_logic_vector(1 downto 0);
internalregisters(conv_integer(indexin)) <= datain; <<<<< in this line datain store in internalregisters(conv_integer(0)) or internalregisters(conv_integer(1)) ?
Re: 8 8 bit resgister
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
clk : in std_logic;
indexin : in std_logic_vector(2 downto 0);
datain : in std_logic_vector(7 downto 0);
A ...
Re: 8 8 bit resgister
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
indexin : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
A : in std_logic_vector(7 downto 0)...
Re: 8 8 bit resgister
i am trying to do 8*8 bit register now.
there are a lot of error in my code, so i need to modify some parts and recompile again. miss, i am not copying so don't be so angry. :D
Re: 8 8 bit resgister
i got it, thanks Marcel Majoor.
here got one and last thing i don't understand.
internalregisters(indexin) <= datain;
datain store in indexin or internalregisters ?
if i am not wrong 'internalregisters' is an array which contain 8*8 bit register right ?
design an 8 bit register
if write = '1' then ....
if read = '1' then.....
what the function for two line above ?
sorry miss, i am learning from here also. please don't call me to your office. :cry:
error (10309): vhdl interface declaration error
can you explain with more detail ?
i want the design contain 8 8-bit registers which can be loaded from an external input and loaded back into one of the eight internal registers, or read externally.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(A, B : in std_logic_vector(7 downto 0);
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
C: out std_logic_vector(7 downto 0));
END alu8bit...
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