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Recent content by trilogy

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    Recommend a nooks for VHDL beginners

    Re: VHDL Beginer If u r really into learning VHDL , some links like http://www.acc-eda.com/vhdlref/refguide/vhdl_keywords/vhdl_keywords.htm can provide u through help for each of the VHDL keywords in detail.
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    What is ASIC and how does it differ from FPGA?

    Re: What is ASIC ? FPGA -field programmable gate array is a really cool stuff, before fabricating u can test ur circuits by just downlaoding them on a FPGA kit and testing them. ASIC on the other side are integrated circcits designed specifically for an ad-hoc purpose- dsp , filters etc. ASIC...
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    Linux Linux ! Linux everywhere

    For newbies Mandrake and UBUNTU are gr8 , no pain to install and use programs, but if u r really a computer systems guy curiious of every thing happenning in ur comp. try Debian, gentoo, Slackware ( warning as wll for these distros)..
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    Can any one tell me the verfication of Design. and lang

    If u want to learm about verification through a tool , I think VCS is good enough. But if u want to learn about how verification actually is done, u have to look for MODEL checking , CTL( complex tree logic),LTL( linear temporal logic), assertion based verification. etc. U can find lots of...
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    What is best tool to learn VHDL?

    For learning VHDL , if one is comfortable with LInux , GHDL is a free tool for Vhdl simuation. Its good.
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    Can any one tell me the verfication of Design. and lang

    first tell me whether your project involves developing some new methodology for verification or you just require tto use verification for some purpose in your project. As for latter case getting verse with any standard verification tool will be enough, else u need to know the various ways of...
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    Can any one tell me the verfication of Design. and lang

    Verification of circuits is a hot property in EDA . Wll their are various tools available for verification by giats like Mentorgraphics, Synopsys. Wll i dont understand what u mean by language for verification. Verification involves various methodologis like CTL, model checking etc.
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    What's different between VHDL and Verilog?

    Re: VHDL & verilog using VHDL one can exactly model the hardware behavior , since VHDL contructs have very wide usage compared to verilog contructs.
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    Best Linux Shell for EDA?

    My idea is Bash is better and Csh users can easily adapt. I also switched frm Solaris - tcsh to Linux-bash. God it is better.
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