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it not possible/ the position of this 3 bits is fix
---------- Post added at 16:57 ---------- Previous post was at 16:55 ----------
in my core 32mb 64mb 128mb 256mb 512mb 1 -2 4 sd 4 8 16 32 sdhc and 64sdxc work similar
determine the frequency. In any case. to generate a sine with a frequency of 1 MHz with an accuracy of 100 points for the period necessary to touch these points at 100 megahertz.
See DDS synthesizer on FPGA
---------- Post added at 11:14 ---------- Previous post was at 11:12 ----------
jumps...
process (main_clk_100meg)
begin
if (main_clk_100meg'event and main_clk_100meg = '1')
then
a_1<= a_0;
a_2<= a_1;
-----------------------------
a_n <= a_n-1;
end if;
end process ;
I'm not a programmer. I can only analyze the process of recording, if you describe the state of the first 10 memory cells. Before and after your download file. To do this, I am interested in the contents of the file.
about the video. Requires intermediate video memory. The size should match the resolution and color depth. For 1024 * 768 and 16 bit color (5-5-6) 1024 * 768 * 2 bytes. Static memory, you can connect yourself. For the dynamic - it is better to take a ready-made controller.
For this controller...
check that
1. read the first 10 memory at address 0.
2. record the first 10 memory at address 0
3. read the first 10 memory at address 0.
Do not forget that memory addressing byte. To read and write to 32 should be addressed to increase by 4.
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