Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by tral

  1. T

    How to covert the spice model to spctre model

    try the following command: spp -convert <netlist.sp> netlist.scs
  2. T

    IC5.0 error when simulating pss

    IC50 pss anaysis problem Pengboy, Maybe firstly, you should check a file in ~/simulation/<cellviewname>/spectre/schematic/psf directory, but I forgot the file name, whether the file is larger than 2,000MB. If it does be true, you should appoint a swapfile in the pss setting window->option
  3. T

    A question about Cadence Virtuoso

    Maybe it's really troublesome for Virtuoso or Diva. But now I think I can solve the problem by Mentor Calibre. Thank you anyway!
  4. T

    A question about Cadence Virtuoso

    I'm a freshman of IC. When using Virtuoso to extract the parasitic parameters of layout, I was told the software could extract just the parasitic RCs of a single wire or several selected wires instead of the whole layout. However, I don't know how to do this. Needing your help:)

Part and Inventory Search

Back
Top