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The UCF file was defined automatically using xilinx user constraints editors, and it is included in the project hence I do not think 1, 2, 3, 4, and 6 are applicable in my case. I have changed the logic definition so that I do not have any async inputs but I am still getting the same problem...
Greetings.
I have designed logic circuitry that has 12 channels with 12 square wave signals at some arbitrary user defined frequency through frequency division by means of a counter and extra circuitry. These 12 frequency division units are connected to the same clock. I implemented this...
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