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Recent content by tigerajs

  1. T

    Why lib file only include FF,TT and SS

    But the process corner includes five types, FF,TT ,SS SF and FS Thanks
  2. T

    VIH, VIL in worst, best and typical case discussion

    From the Spec, we can see the VIH and VIL has the relation ship with VDD. My question is that VDD may be different in worst, best and typical case, such as 0.9V,0.7V and 0.8v. Is VIH or VIL different in these three case or just use the typical VDD 0.8v? Thanks
  3. T

    Who has the lora modem spec

    The lora is a patent, who has the spec of lora modem , i cannot find anywhere, thanks.
  4. T

    what does the headroom mean for audio DRC

    for DRC module , four MSB bits are add the input audio data, and the SNR add 24db. what does this mean and how to add the headroom , thanks.
  5. T

    How to deal with this DFT warning

    The shfit_enable used the internal module pin for pin mux, and after syn, it display as follows: Cannot idealize the test signal(DFT-199) How to solve it, or ignore this warning? Thanks
  6. T

    why the verilog_xl don't support always@(*)

    how to fix it , thanks.
  7. T

    The flow of primetime for bottom-up syn

    run pt for each sub module or only run the top module use every SDC,thanks
  8. T

    DFT simulation problem help

    sim report error: // *** ERROR during scan pattern 0 (detected during load of pattern 1) 0 1 0 (exp=1, got=0) // pin scan_so, scan cell 0, T= 957240.00 ns 0 1 2 (exp=0, got=1) // pin scan_so, scan cell 2, T= 957440.00 ns 0 1 4 (exp=1, got=0) // pin scan_so, scan cell 4, T=...
  9. T

    ATPG issue. Test patterns failed in simulation .

    I still can't sovle it , can anyone help me , thanks.
  10. T

    DFT simulation problem help

    TETRAMAX generate test pattern and use ncverilog to sim，take no timing info, but it report error, what is the question , thanks,
  11. T

    How to run DC DFT for bottom-up syn

    syn some blocks , BLK1.BLK2,BLK3 and do DFT，DFT input is scan_si,scan_en, and out is scan_so. And do the syn of the top module ，use 2 way to get 2 results （1）Use BLK1.BLK2,BLK3 ddc as library to read ，then set_dont_touch BLK1.BLK2,BLK3, after syn to get coverage ，only 38%。 BLK1. BLK2, BLK3 port...
  12. T

    How to run DFT for both async reset and set circuit

    insert DFT
  13. T

    what is main function of hold_l for MBIST

    It is used together with debugz, how is the mian time of them, thanks.
  14. T

    How to run DFT for both async reset and set circuit

    what is the command for Synopsys DFT
  15. T

    How to run LEC after bottom-up syn

    how to set the command for formality
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