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um. actually i want to make it. if u go to this site. u can see it.
https://cafe.naver.com/veryveryverilog/8
but i dont know how i make it . ( verilog)
input D;
output Q;
for example,
Q=D; this is possible.
but D=Q; this is not possible.
huhuhuhuhu....
i made a simple D-flip flop.
=========================
module dff(Q,C,CE,CLR,D);
output Q;
input C;
input CE;
input CLR;
input D;
reg Q;
always@(posedge C)
Q=D;
endmodule
======================
but i wanna make a feedback D-flip flop.
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