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Hi ic_qiand ;
1-temp[3] [1:0] means select only the first two bits from element number 3 not the whole 8 bits.
2-always(*) it is a feature in verilog 2001 insead of using sensitivity lit
Hi all,
i have some question,
1- always @ * is not syntheisable , why?
2- if i have
wire [7:0] temp [3:0];
wire [1:0] temp1;
assign temp1 = temp[3] [1:0]; is not suntheisable why?
and what is the work around?
IN Q3D extractor if on he edge of silicon materials i put a box of copper does it considered as ground?
if not how to assign multiple ground in a design//
Re: HFSS - How can I create a material with a gradient index
if u opened the materials window u will find {frequency dependent materials) just marked it and u can deal with eipslon as a function of f
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