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Recent content by TheBrian

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    Error on counting distance between 2 rising edges

    i just tried to make a dummy signal to replace clk_div, and the program works.. :/
  2. T

    Error on counting distance between 2 rising edges

    I'm trying to count distance between two rising edges. i found a problem when i install the program into my Xilinx Spartan 3 starter kit, which the output is different from what i expected. The process is simply: clk_div is an enable signal and sync with the clk. The simulation result using...
  3. T

    Spartan 3 PROM Verification problem

    http://www.digilentinc.com/Products/Detail.cfm?Prod=ADEPT maybe that will help,,
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    floating point to binary in VHDL

    floating point to binary i'm a newbie at vhdl, but i think i'd rather convert it to 4 bits with other signal as a flag.. but it depends on how i want to use it.. can i do that??
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    Suggetions: Want to buy an FPGA

    http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD i think that should be sufficient..
  6. T

    problem with ISE simulator

    a project was once just gone, and often i couldnt open my projects after i generate the programming file!! it said my project is not supported by (bla.. blaa..) and need to be updated, and it said something about Leornardo Spectrum.. O i hate Xilinx ISE.. :P
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    inverted pendulum - design of digital PID

    i'm doing a similiar project using Xillinx FPGA and rotary encoder as feedback.. how's your result??

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