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Maybe this floating gate error is a chip level DRC and not enabled in the local DRC you're running. In any kit, when you run DRC on circuit level (not chip level), not all the DRC rules are enabled, for instance, the metal intensities, or the via arrays DFMs are not enabled, and the drc check...
Hi,
unmapped key points will lead to non-equivalence in my experience. From what I see, it might be related to the black boxing. Use black boxing specifically with the module names, I prefer using the NoTranslateModule. You can use "report black box" to ensure that they are boxed properly.
There is a section in Synopsys DC compiler manual about the max_fanout variable, I am not sure how to set it though ... I've tried "set max_fanout <value>" before and it didn't work well with me.
Hi,
I am designing an LC VCO , and when I plot the tuning sensitivity plot, i.e. frequency - voltage curve (varactor control) , with a larger number of steps, I get discontinuities in the curve, and errors at some values ... in other words, at couple of voltage values, the frequency is much...
Hi ,
I am designing an LC VCO ... So I need a varactor ... when I connect the varactors RIGHT, I mean the positive terminals to oscillating nets and the -ve terminal to ground, the oscillating frequency does not vary with varying control voltage ... So, I folded the varactors, it worked ! ...
Hi,
I'm designing an RF frequency synthesizer (sigma-delta fractional-N PLL) for an LTE sys. , in system level design, I need the synthesizer specifications , how can I determine the Settling Time spec ?? ... I can't find any condition in LTE standard on how fast can the system changes the...
Exactly as you said [memory changes] + the value of SP will be decreased by 2 [Register Changes]
Check if there's an empty place in your stack segment (view the memory in the emulator and notice byte by byte change in this section of code if possible) , check if there's any segments overlap...
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