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Recent content by thaolam

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    How to declare bidirectional bus in verilog testbench?

    Hi, I am creating testbench for SRAM. When WREN_N=0 && BFRD=0 && OE=0, SRAM will do write operation with input Data is D[7:0]. When WREN_N=1 && BFRD=1 && OE=1, SRAM will do read operation with output Data is D[7:0]. WREN_N: write enable pin, active at low BFRD: read enable pin, active at...

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