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hi all;
i have this code for a 5-bits binary counter :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY counter IS
PORT ( count : OUT unsigned (4 DOWNTO 0);
load : IN STD_LOGIC;
pre :IN unsigned (4 DOWNTO 0);
Clk : IN...
Hi all,
I am tried to write VHDL code for 1 to 8 Demux and that's what i finish with it
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN...
Plz help. Vhdl code
I want a structural VHDL code of 1 to 16 Demultiplexers. with an active low Enable signal using 1 to 2 Demultiplexer. [ use Generate statement]
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Also I need a structure and behavior VHDL code of 5-bits binary...
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