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I'm a bit confused here. The ADDR_WIDTH is defined as :
parameter ADDR_WIDTH : {M_PORTS{{M_REGIONS{32'd24}}}},
My understanding is it's an array of array of 32bit integer with default values of 24 for each element.
In the testbench provided with the IP core, they assigned the values like...
What I want to do, is to instanciate propritary IP block coded in Verilog in my VHDL code. My question is how I define the M_ADDR_WIDTH parameter in my component declaration in VHDL?
The way I understand it, M_ADDR_WIDTH is a parameter that defines the address width of multiple master ports of...
I have trouble to understand this following replicate operation in Verilog. What will be the value of ADDR_WIDTH, READ, WRITE parameters?
module xyz #(
parameter SLAVE_PORTS = 2,
parameter MASTER_PORTS = 4...
Thanks for your feedback vGoodtimes.
I have realized that I can't use a MMCM because the clock from the chip is not continuous. Also, my FPGA doesn't have ODELAY primitives. So it lets me little option as to use IDELAY for the inputs and the clock or to invert the clock for the ouput FFs...
I have a chip connected to my FPGA which provide the clock with the bidirectionnal data bus. The clock frequency is 100MHz. Here's a view of my implementation for the dataout from the FPGA to the chip.
The clock of U0 is connected directly to an IBUF and BUF. After my implementation, I...
iii, jj, kk and ll don't have the same initial value. This is why they are not in phase.
signal ii,iii: integer :=0 ;
signal jj: integer :=30 ;
signal kk: integer :=60 ;
signal ll: integer :=90 ;
At t=0 your sine2 memory is uninitialized. sine2 memory is written 1 byte at a time on each clock cycle. So after 360 clk cycles sine2 will be fully written. In your simulation, check how sine2 memory is filled.
You need to initialize sine2 with random value the same way you did with sine...
Your block diagram is incomplete. From your drawing, the SPI master has 4 ports while the code for it has over 20 ports. The same with the SPI slave.
Match both your drawing and the code, then post it again.
While you will be doing this, you will realize that the ports of the modules are...
From the code above, there's no chance. The uart pins are not mapped on the top module.
Do you realize that the code you posted is for simulation? Did you ever simulated it before?
I will ask as the other members of this forum asked. Post the block diagram of your design. We want to see...
What makes you think that the problem is in the UCF?
From the code you posted in #25 for the master and the slave, there are a lot ports that must be connected to some user logic in the FPGA to control the cores. We haven't seen this code yet. I'm thinking that you only copy-pasted these codes...
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