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you gays can refer to MiddleBrook's paper for the problem. In my design, Z is as dominant pole and is connected to a 4pf compensation capacitor ( not show in the attachment), when break this node, where the compensation capacitor can be loacted?? the opamp output side? or the PMOS gate input...
fundamentally, Z can be break to run ac simulation,
but when Z is the dominant pole, break z may lead to inaccuracy in PM and bandwidth. Additionally, it is hard to determine "equvalent" load.
if the opamp is used in dc applications such as bandgap, i think psrr=50db at 1Mhz is not necessary,unless the circuit is disturbed by high frequency noise. of course, in high gain opamp, the psrr also is very high, if the bandwidth is set to high value, it is not hard to get psrr=50db in 1MHZ
AS shown in the attachment is the common used bandgap, i want to simulate ac response to gain PM, when i disconnect the input of amplifier (X OR Y). the transfer function has positive sign and the PHASE of the open loop gain is from 0 to 180 when frequency is incresing. but when disconnect the...
mos capacitor drain source
You can obtain the equivelent capacitance of MOSCAP by HSPICE transient simulation. caculate the total charge (Q) stored in the CAP in fixed voltage range (Vr), then the C=Q/Vr .
Re: Opamp Design Help..
You can also refer to IEEE papers ,such as
B. Sekerkiran, “A Compact Rail-to-Rail Output
Stage for CMOS Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, vol. 34, pp. 107-110, 1999.
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