Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by tarmember

  1. T

    startup or BIG Company

    Hi , I would like to advise you to join the start up company. At the start up you will go through all the phase of the product design cycle/design cycle of the project. While in the big companies, work is distributed equally in the groups. So start with the start up and then be master in...
  2. T

    How to display real time and date in verilog?

    you can use $system("<unix commands>") in your verilog code to print the date and the time in your log file. But please check first that does your simulator have $system function or not. NCverilog and VCS have this function. Hope this helps. Regards
  3. T

    doubt in Synopsys DC and VCS

    As per my knowledge latest version of DC is 2006.06 and latest version of VCS is also 2006.06.
  4. T

    why 50% duty cycle is needed ?

    The 50% duty cycle has also relationship with the power. If you have a 50 % duty cycle then less power is consumed by clock generator then that of the consumed by lesser/higher duty cycle.(this is related to Fourier transform of square wave). Hope this helps you.... Regards, Tarang
  5. T

    verilog scheduling semantics

    Active event as per Verilog "stratified event queue".
  6. T

    RTL coding guidelines ?

    Hi VJ, RTL coding guide lines needs to be followe to avoid the the simulation and synthesis mismatch. And also for the desired synthesis results. You search on the web, you will get many documents on it. I would suggest you to refere the papers published by Cliff Cumming on verilog coding...
  7. T

    What is the Race condition in Verilog?

    Re: Race ? Hi VJ, There are two kind of race. One with the digital hardware(i.e. in flip flop ) and second is with the verilog simulation. Both situations are considered as a race condition. Hope this helps... Let me know if you want to know in details...
  8. T

    What's the best Verilog simulation software?

    Re: verilog software If you are student then it might be possible that your school/college participated in University programme offered by almost all EDA tool vendors. You can check within your college/school lab. that student version is available or not.
  9. T

    What's the best Verilog simulation software?

    Re: verilog software if possible provide some links for student version!! thanks -Shiv Go to www.icarus.com. It is free and fairly good simulator for verilog. Best tools for verilog e.g. NCverilog,VCS,Modelsim are not free.
  10. T

    Where to learn the asic design process

    Yes. CDAC-pune offers this type of cources. It is callled Post Diploma in VLSI. Many other private institutes are available e.g. IIIT,Hyderabad. For more details refer course catalog.
  11. T

    The major difference between ASIC design and FPGA design!

    Re: The major difference between ASIC design and FPGA design The FPGA is a basically a sea or configurable logic cells. This configurable cells can be configured as per need. And all the configurable logic cells are connected to gether to bring up the whole functionaly via a programmable matrix...
  12. T

    What's the use of Elaborator in NC-SIM?

    Re: regarding NC-SIM As per my understanding the elaborate means that (in context of HDL compilers ) is to unroll (~ = making a single executable from all the compiled fidle) the whole code and convert it into a low level binaries/librarries. Hope this helps. Bye the way Not only NC-sim has a...
See more

Part and Inventory Search

Back
Top