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Am I supposed to make some turns in my life by reading your reply!!!!??!! when you say there is no much science to it.. you must have considered skipping all the journals and transaction papers. The thing is most of them are related to pure digital domain whereas I need something to quote from...
Hello everyone,
I am doing my thesis work on developing a design methodology which reduces the post layout simulation time for large analog designs.
I cannot find a proper literature that already talks about it. Whenever I search I get articles, books on Analog verification, mixed-signal...
Hi, I also saw that a bit later. But I do not know how does redhawk pick up the margin values? Is there any specific keyword. I could not find one in the manual.
Hi,
Sorry, It is not possible for me to share the input files as I signed a NDA. Can you guide me from where should I start debugging. I already looked into the log file. BUt it was not helpful. Any ideas would be appreciated!!
Thanks
Hello everyone,
I am new to the tool Apache RedHawk. I set up power analysis for Static and Dynamic (only vectorless) mode. But I am facing a strange problem. During Static analysis, I have values of wire & via voltage drops. But, during the dynamic analysis, I have no values for voltage drop...
Hi All,
I have my DC and small-signal AC analysis from TCAD Sentaurus. Now, I have to plot transit frequency vs. drain current.
I am calculating transient frequency in two ways.
1. ft= gm/(2*pi*cgs)
2. ft= f0/imag(y21/y11); f0=3e8 also used during simulation.
Now, I have two different graphs...
Hi freebird,
Thanks for reply.
- you are correct, the nominal temperature is found elsewhere and it is 25 degC.
However, can you tell me, what is meant by *|NET net8 1.7039e-16? Is it the capacitance value found in net8? If so, what kind of cap?
again, thanks in advance.
Hi, I am new to post layout simulation. I am having trouble in interpreting the extracted netlist. Can someone please translate the statements to English language!!!
*|NET in 2.04548e-17
*|I (XI5:A XI5 A X 0.0 0.2867 0.945)
*|I (XI9:Z XI9 Z X 0.0 6.562 0.945)
*|P (in X 0.0 6.562 0.945)
cin|0...
Hi Amit,
I already looked at this solution before posting. I need some debugging in for my code. I do not know where is the problem. The twiddle factor computation, the real, imaginary parts all seems ok. Can you help? Thanks in advance!
Hello,
I have a project submission on DIF FFT in C code. I have tried so many things but can not get the code to work.
#include "fft.h"
int fix_fft(fixed fr[], fixed fi[], int m, int inverse)
{
int mr,nn,i,j,l,k,istep, n, scale, shift,twid;
fixed qr,qi; //even input
fixed tr,ti; //odd...
Hi,
I am just getting more and more confused.
Is there any general formula for calculating overflow that would work for signed and unsigned, addition and subtraction.
If possible, please an example with explanation would be really appreciated.
TIA.
I am trying to implement add ALU in verilog.
I have to set the overflow flag from addition.
What I have got from googling is, if the operation is carried on 2's complement,
overflow = c(i) xor c(i-1)
But, my confusion is as follows:
let's say I am adding 16'hFFFF + 16'hFFFF
so, i should get an...
Re: 16-bit Processor Design in Verilog
Wow!!!
Cleared a lot of things!! thanks a lot.
Just one more question:
to check whether my operand size is more than ALU, do I have to perform any checking??
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