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Hi,
I am in learning phase of both TCL and Linux Bash scripting.
I have noticed that many of the syntax of TCL are very much similar to Bash scripting.
So is there any connection between the two, as Linux I use as an operating system and TCL I use to automate software processes.
Hi,
I am working in a large team. I am at Digital side, and working with ModelSim. I have made many test cases for different system aspects.
The guy working on Analog side is working with Cadence Virtuoso.
The files: Testcase + include files + testbench + system design files, I have already...
Thanks for replies.
Actually the source of my confusion is as follows.
Here is a generate code:
generate
genvar row;
for (row=0;row<5;row=row+1) begin : I_ROW
AND CU (.a(row),.b(row),.c(row));
genvar j;
for (j=0;j<8;j=j+1) begin : CELL
OR LA...
Hi,
Please see the code below:
module ha ( input a, b,
output sum, cout);
assign sum = a ^ b;
assign cout = a & b;
endmodule
module my_design
#(parameter N=4)
( input [N-1:0] a, b,
output [N-1:0] sum, cout);
generate
for (i = 0; i < N; i = i +...
Guys, I need a board in large quantities(10 or more). The problem with this board is : they are long obsolete. Now, where I should search for these boards? I have checked Xilinx store, Ebay, Amazon, Digikey, Mouser, Google.
But of no avail.
May it happen that some guys may be having old stocks...
Thanks for replay.
In Section 9.4.2.1 of same document:
The logical OR of any number of events can be expressed so that the occurrence of any one of the events
triggers the execution of the procedural statement that follows it. The keyword or or a comma character (,)
is used as an event...
The difference between '|' operator and keyword 'or'
Hi,
I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
In most of the always blocks, the keyword 'or' is used, and in if statements, either '|'...
Actually the thing is, I was more alarmed by the Intel's strategy. They are not progressing with their traditional processors very fast(I think due to frequency + multicore bottle neck). But if they are not putting too much energies on traditional processors(I know they bought Altera recently...
I am thinking(in fact worried about) a topic that I have no answer for. That's why, I am posting here, and inviting international intelligentsia to come and share views.
First my background: I am an ASIC designer who has just started my career in ASIC design industry. I am doing codes in...
I was designing a system, and the customer wanted to operate it on 10MHz.
There was a 10 Millisecond counter in that design, so I applied a 17 bit counter that gives a tick every 10 milliseconds based on this frequency. The code was like that:
always @(negedge sys_rst_n or posedge sys_clk)...
That worked. Just mentioning here for the future reference of others.
@FvM The reference that you gave is the reference that explains what is printing with minimum size. Thanks.
Hi,
Please see the code below:
$fwrite(WglFile, "\tFREFH := input[%dnS:S];", wgl_t_timeplate_FREFH, "\n");
here wgl_t_timeplate_FREFH is of integer type.
When I run this line, the output is like :
FREFH := input[ 0nS:S];
Please notice the space between bracket start and...
Hi,
I have a Systemverilog Script that is generating WGL script for every testcase that I run for simulation using TCL (do files). The issue is, in Modelsim everything is ideal(no delays)). And I think the same will be reflected in generated WGL files, as by inspecting WGL it is clear that in...
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